Caeleste is looking for a Professional Analog Designer
As a project leader, you will lead the design of novel CMOS image sensors. You have the feeling for the challenges associated with mixed mode analog-digital design. You will be in intense interaction with your peer technical experts. You will have significant responsibility and autonomy in the team. Your tasks include a broad scope ranging from image sensor design and evaluation, research on better circuits and topologies, design methodologies, design correctness and verification, project management, travelling and partner interaction and project management.
Minimal requirements
- 5+ years of relevant experience in analog, mixed mode or imager development
- Demonstrated experience as a design lead for complex analog or mixed-signal chips
- Good background in analog electronics, and over-the-wall interest in physics and sciences
- MS in Electronics Engineering or equivalent by experience or vocation
- Creativity, analytical mind and problem solving skills
- Good communication skills in writing, presenting and customer interaction
- Solidar teamplayer who assumes the project management
Additional skills that are of interest
- Experience in image sensor design, i-SoC, testing, camera or instrument design
- Experience with management of IC development projects
- Background in Silicon processing
- Background in Optics and solid-state physics
For all your questions, please contact
Patrick Henckes, CEO patrick.henckes@caeleste.be Caeleste CVBA Generaal Capiaumontstraat 11 2600 Antwerpen+32 3 3361675
you can download this job description in pdf format.
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Caeleste successfully designed and tested a SPAD (single photon avalanche diode) photon counting image sensor. After a first successful demonstration with hybrid avalanche photodiode, Caeleste introduces integrated, compact pixels with avalanche photodiodes, allowing large resolution image sensor with single photon detection capabilities in the visible spectrum range. The demonstrated array has 32×32 pixels on a 30µm pitch, in TSMC 0.18µm technology. Several SPAD pixel variants are optimized for QE, dark count and afterpulsing.
to know more about this technology, do not hesitate to contact us.
Caeleste hits the news with a short presentation of its recent work published on image-sensors-world.
“Caeleste publications page has been updated to include the latest CNES Workshop 2011 presentations. The most interesting one is “A 0.5 noise electrons CMOS pixel” by Bart Dierickx, Nayera Ahmed, and Benoit Dupont. The presentation explains the 1/f and RTS noise reduction principle by cycling the pMOSFET between accumulation and inversion”
Read more… and discuss on image-sensors-world.
ESO and Caeleste publication at CNES Workshop on High performance CMOS image sensors
ESO published results of a joint project with e2v and Caeleste at the CNES conference on High performance CMOS image sensors. it describes a “High QE, Thinned Backside-Illuminated, 3e- RoN, Fast 700fps, 1760×1760 Pixels Wave-Front Sensor Imager with Highly Parallel Readout”
With courtesy of ESO, we are pleased to make the presentation available for download from this link.
you can find all our papers in our publication section.